1 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator description m66242 integrated circuit has four 12-bit pwm (pulse width modulation) circuits which are built by using the cmos (complementary metal oxide semiconductor) process. this ic controls pwm waveform by adjusting the h width according to serial data sent from mcu (micro controller unit) or other device. each channel can be independently con- trolled. high-resolution digital-analog converter can be formed eas- ily by connecting a low-pass filter circuit to the output pins of this circuit. features ? built-in four 12-bit high-resolution pulse width modulation circuits ? easy digital-analog conversion C quick output waveform smoothing control by 1.22mv possible per step (v cc =5v) ? serial data input ? h level width setting type ? 4 independently controlled channels ? all 4 channels reset by reset input (r) high-impedance sta- tus after reset ? all 4 channels controlled by output control input (oc) ? settings take effect after ongoing cycle is completed ? input: ttl level ? output: cmos 3-state output output current i o = 4ma ?v cc =5v 10% pin configuration (top view) application ? analog signal control in televisions and audio systems ? control of lamps, heaters and motors ? for software servo in home appliances and industrial ma- chinery block diagram (each channel) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 cs r wr s in s clk oc gnd v cc pwm1 pwm2 pwm3 pwm4 x out x in outline m66242p/fp clock output clock input chip select reset write control serial data input write clock output control output 14p4 14p2n-a 4 5 1 2 3 6 7 9 8 10 11 12 13 14 input register control circuit lower byte register upper byte register pwm register 8-bit pwm circuit 4-bit-rate multiplier 12-bit pwm circuit to other channels 1/2 divider oscillation circuit s in s clk cs r wr oc gnd x out x in pwm4 pwm3 pwm2 pwm1 v cc
2 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator subsections t, each of which has this basic waveform. among them, those which are designated by the 4-bit-rate multiplier are conditioned to have a h width that is longer by t . the lower 4 bits of pwm data are used to specify those subsec- tions (t m ). the waveform of other subsections remains un- changed. a pwm waveform (12-bit resolution) is a combination of two types of waveforms which are different in h width, as de- scribed above. when output control input oc is h, the output of every channel turns high-impedance from the next cycle. when reset input r is l, the output of every channel turns high-impedance as soon as the ongoing cycle is completed, and pwm data of all channels is reset. if r input is changed from l to h, the next cycle starts, however, the output of the channels remains high-impedance. to enable output, rewrite input data for each channel. **)f xin : clock x in repeat frequency function the pwm output waveform of each channel is controlled by taking in pwm data from mcu or other device via serial data input s in . twelve-bit pwm data is input being divided between upper 8 bits (upper byte) and lower 4 bits. the lower 4-bit data is combined with command data such as channel designation and input as 8-bit data (lower byte). the lower byte should be written first, and then the upper byte. even if only the upper byte is to be changed, rewrite from the lower byte. the pwm waveform changes according to the new setting from the next cycle. one cycle of pwm waveform (4096 divisions; 12-bit resolu- tion) are divided into 16 (2 4 ) subsections t. each subsection consists of 256 (2 8 ; 8-bit resolution) minimum bits t (=2/ f xin **). one subsection t consists of a 8-bit pwm waveform (basic waveform). the h width of this waveform is determined ac- cording to the upper 8 bits of pwm data. one cycle has 16 pin descriptions functions l: all 4 channels put in high impedance state. l: communication with mcu becomes possible. wr, s in and s clk put in enable state. l: serial data written. l-to-h edge: written data stored in upper or lower byte. inputs 8-bit serial data from mcu synchronously with clock pulses. inputs sync clock pulses for 8-bit serial data writing. h: all 4 channels put in high-impedance state. outputs pwm waveform. (cmos 3-state output) inputs/outputs signals generated by clock signal generation circuit. oscillation frequency is determined by connecting ceramic or quartz resonator between x in and x out . the frequency of internal clock (pwm timing clock) signals is the 1/2 divider of the frequency input from clock input x in . when external clock signals are used, connect clock generator to x in pin and leave x out open. pin r cs wr s in s clk oc pwm1~pwm4 x in x out name reset input chip select input write control input serial data input write clock input output control input pwm outputs 1 thru 4 clock input clock output input/output input input input input input input output input output
3 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator (1) upper byte resister (2) lower byte resister fig. 1 upper and lower byte resister makeup mode input serial data lower byte data b7 b6 b5 b4 1 b2 b1 0 b7 b6 b5 b4 1 b2 b1 1 xx x x0b2b1x upper byte data CCCC b7 b6 b5 b4 b3 b2 b1 b1 CCCC pwm data setting (output enable) lower 4-bit data setting 12-bit data setting output disable table 1 mode selection pwm register b3-b0 0000 0001 0010 0100 1000 1111 subsections t m whose h width is increased by t (m =0 thru 15) nothing m=8 m=4, 12 m=2, 6, 10, 14 m=1, 3, 5, 7, 9, 11, 13, 15 m=1~15 (m 1 0) number of subsections 0 1 2 4 8 15 table 2 patterns of lower 4 bits and subsections whose h width is increased b7 b6 b5 b4 b3 b2 b1 b0 pwm output h width setting bits (upper 8 bits: b11 thru b4) b7 b6 b5 b4 b3 b2 b1 b0 write data designation bit 0: lower byte only 1: both lower and upper bytes pwm output select bit 00: pwm 1 01: pwm 2 10: pwm 3 11: pwm 4 output control select bit 0: output disable (bits b7~b4 and b0 are ignored.) 1: output enable pwm output h width setting bits (lower 4 bits: b3 to b0)
4 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator operation serial data input when chip select cs is l and write control input wr is l, data input to s in at the edge where write clock input s clk sta- tus shifts from l to h is written. (see fig. 3.) at the edge where wr rises from l to h, the latest 8-bit data writing is completed, and input data is stored in lower (or upper) byte register. when writing on the lower byte or writing on both upper and lower bytes is completed, data on the lower byte register or, in the latter case, data on both lower and upper byte registers is written on the pwm register of the channel designated by lower bytes b2 and b1. all setting pro- cess ends with this writing, and pwm waveform changes ac- cording to the setting from the next cycle. pwm waveform output (1) 12-bit pwm output one pwm waveform cycle is divided into 16(2 4 ) subsec- tions t, and each subsection is further divided into 256 (2 8 ) minimum resolution bits t (= 2/f xin ) the h width of subsection t basic waveform is deter- mined by the upper 8 bits of pwm data. (in fig. 2 above, h width is 4a 16 = 74 t ) among these 16 subsections t, subsections t m designated by the lower 4 bits of pwm data have h width that is longer by t . [in fig. 2 above, the h width of designated 6 subsections (m =2, 4, 6, 10, 12 and 14) is 4b 16 = 75 t .] fig. 2 pwm waveform output example (input data: 4a6 16) 01001010 0110???? 010010100110 b7 b0 b7 b0 b11 b4 b3 b0 upper byte register lower byte register pwm register 4a6 16 determines h width of basic waveform (in this case, h width is 4a 16 = 74) determines subsections t m whose h width is increased by the minimum bit width of t (refer to table 2.) (in this case, m = 2, 4, 6, 10, 12 and 14.) basic waveform (e.g. when f xin is 4 mhz, = 0.5 m s) t 74 t t = 2 f xin one subsection t = t 256 (8-bit resolution) designated subsection t m (in this case, m = 2, 4, 6, 10, 12 and 14.) t output waveform subsection one cycle t 0 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 15 t 74 t 75 t 74 t 74 t
5 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator the h width of undesignated subsections remains un- changed. as explained above, one cycle of waveform is a combina- tion of two waveforms different in the h width. (in fig. 2 above, one cycle consists of 10 subsections whose h width is 74 t and 6 subsections whose h width is 75 t .) note: it is impossible to set one whole cycle to h level. (2) 8-bit pwm output as can be seen from the 12-bit pwm waveform output process as described above, 8-bit resolution pwm wave- form can be output by fixing the lower 4 bits of pwm data to 0000 2 . all subsections from t 10 to t 15 have the h width as deter- mined by the upper 8 bits of pwm data. note: it is impossible to set one whole cycle to h level. output control (1) serial data input by using data on lower byte register b3 (output control se- lection bit), output of each channel can be controlled inde- pendently. the state of the selected pwm output changes after the completion of the ongoing cycle. when b3 is set 0, lower byte register b0 (write data desig- nation bit) is reset. do not write on upper byte in this case. (2) output control input the status of all 4 channel outputs during a cycle is deter- mined depending on the status of output control input oc at the start of the cycle. (see fig. 6.) even when output is in a high-impedance state, data on each pwm register is retained, and data can be rewritten. (3) reset when reset input r turns l, all operation is reset as soon as the ongoing cycle is completed: the outputs of all 4 channels turns high-impedance. the pwm register of each channel is reset. when r is shifted from l to h, a next cycle starts, and data writing becomes possible. however, outputs stay in the high-impedance state. (see fig. 6.) to resume output, write input data for each channel. initial state after power-on, outputs and pwm register data are unstable. (1) reset reset input r is kept on l level for more than one cycle (2.048ms when f xin is 4 mhz) or more, this integrated cir- cuit is put in a reset state. if stabilization needs more time, e. g. when a quartz reso- nator is used, keep r on l level for an adequate period of time. (2) serial data input when starting using this integrated circuit without reset- ting, input false lower byte data (b0 =0) to stabilize lower byte register b0 data, and then input normal data. fig. 3 serial data write timing pwm output b0 b1 b2 b3 b4 b5 b6 b7 wr s in s clk ongoing cycle next cycle
6 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator pwm setting data fig. 5 8-bit pwm waveform output example fig. 4 12-bit pwm waveform output example pwm setting data t t= 2 f xin 2 12 1 cycle 000 16 001 16 002 16 003 16 00e 16 00f 16 010 16 011 16 012 16 013 16 963 16 ffd 16 ffe 16 fff 16 t 0 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 15 t t 150 t t t t t t t t 150 t t 255 t t t t t 000 16 010 16 020 16 fe0 16 ff0 16 1 cycle t 0 t 13 t 15 t 1 t 2 t 3 t 14 t 255 t t 2 t 254 ttt ttt t 2 t 2 t 2 t 2 t 2 t 2 t 254 t 254 t 254 t 254 t 254 t 254 t 255 t 255 t 255 t 255 t 255 t 255
7 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator fig. 7 pwm setting flow chart fig. 6 output control timing chart r oc cs wr s in data internal signal f (cycle start signal) pwm output high-impedance 1cycle high-impedance start reset set lower byte set upper byte setting complete? output enable pwm output change settings? repeat series of operation a stop oc = l, or lower byte b3 = 1 r = l wr = l wr = l b0 = ? a yes yes no no 1 0
8 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator conditions when output is h or under high-impedance condition v i <0v v i >v cc v o <0v v o >v cc v cc , gnd ratings C0.5 ~ +7.0 C0.5 ~ v cc + 0.5 C0.5 ~ v cc + 0.5 C10 10 C10 10 15 40 150 C65 ~ 150 symbol v cc v i v o i ik i ok i o i cc p d t stg parameter supply voltage input voltage output voltage input protection diode current output parasite diode current output current supply/gnd current power dissipation storage temperature unit v v v ma ma ma ma mw ?c absolute maximum ratings (ta = C20?c ~ 75?c unless otherwise noted) recommended operational conditions symbol v cc v ih v il i oh i ol t opr parameter supply voltage h input voltage l input voltage h output current l output current ambient temperature limits min. 4.5 0.8v cc 2.0 0 0 0 0 C20 typ. 5 max. 5.5 v cc v cc 0.2v cc 0.8 C4 4 75 unit v v v v v ma ma ?c x in other input x in other input pwm1~4 v oh 3 v cc C0.8 pwm1~4 v ol 0.5 symbol v oh v ol i ih i il i ozh i ozl i cc d i cc parameter h output voltage l output voltage h input current l input current h output current under off condition l output current under off condition power dissipation maximum quiescent power dissipation electrical characteristics (t a = C20?c ~ 75 c, v cc = 5v 10% unless otherwise noted) max. 0.5 1.0 C1.0 5.0 C5.0 40 2.9 unit v v m a m a m a m a m a ma typ. 4.7 0.2 0.4 min. v cc C0.8 limits test conditions i oh =C4ma i ol =4ma v i =v cc v i =gnd v o =v cc v o =gnd v i =v cc , gnd, i o =0 m a v i =2.4, 0.4v (note 1) pwm1~4 pwm1~4 note 1: only one input (excluding x in ) should be set to this voltage. other inputs should be connected to vcc or gnd.
9 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator symbol f max t plh t phl parameter output lCh, hCl switching characteristics (t a = C20?c ~ 75 c, v cc = 5v 10% unless otherwise noted) max. 100 100 unit mhz ns ns typ.* 25 25 25 min. 16 limits test conditions c l =50pf (note 2) x in x in pwm1~4 h : standard values are measured under conditions of v cc = 5v and ta = 25?c. note 2: test circuit (1) pulse generator (pg) characteristics: t r =t f =6ns (2) capacitance c l includes connection floating capacitance and probe input capacitance. tested element p.g. 50 w gnd c l v cc input output symbol t c(x) t w(xh) t w(xl) t w(s) t wrh t su(cs) t su(wr) t su(s) t h(cs) t h(wr) t h(s) t h(sclk) t r t f parameter x in cycle time x in h pulse width x in l pulse width s clk pulse width wr h hold time cs l setup time after wr wr l setup time after s clk - s in setup time after s clk - cs l hold time after wr wr l hold time after s clk - s in hold time after s clk - s clk hold time after wr - input rise time input fall time timing characteristics (t a = C20?c ~ 75 c, v cc = 5v 10% unless otherwise noted) max. 25 25 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns typ.* 40 20 10 5 10 5 5 10 5 5 5 min. 62.5 32.5 30 30 6tc (x) 30 30 50 30 10 10 30 limits test conditions h : standard values are measured under conditions of v cc = 5v and ta = 25?c.
10 mitsubishi digital assp ? m66242p/fp 4-ch 12-bit pwm generator timing charts note 3: (1) shaded portions indicate that switching is possible during those periods. (2) pwm outputs 1 to 4 change synchronously with internal clock signals f . the frequency of these signals is the 1/2 divider of the frequency input from x in . application example (combination with electronic control m5283p for amplifier system) t su(cs) 1.3v 1.3v t h(cs) 1.3v t wrh t h(wr) t h(sclk) t su(wr) t w(s) t w(s) cs t su(s) t c(x) t w(xh) t w(xl) 50% 50% t plh t phl 0v 3v 0v 3v 0v 3v 0v 3v 0v v cc v oh v ol wr s clk s in x in pwm1~4 (internal clock) t h(s) 1.3v f 1.3v 1.3v 1.3v 1.3v 1.3v 50% 50% cd fm dat av mcu m66242p/fp pwm graphic equalizer electronic control m5283p power amplifier speaker control microcomputer buffer/low-pass filter
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